1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices used for various electronic equipment and devices. More particularly, the invention relates to a method of fabricating a semiconductor device provided with an insulating wall in the portion where the semiconductor area containing impurity and the electrodes are in contact.
2. Related Background Art
In recent years, along with the evolution of semiconductor integrated circuits which have increasingly become more highly integrated, the super-miniaturization of elements are advancing creaselessly.
At present, taking the emitter size of a bipolar transistor (the minimum machinining dimension) as an example, the miniaturization has advanced to the extent that it is approximately 1.0 to 1.5 .mu.m by the conventional method using photolithography and 0.5 to 1.0 .mu.m by the method using self-alignment. Therefore, the contact size formed in the emitter has also become approximately 0.5 to 0.8 .mu.m making it necessary to use an exposure apparatus at its resolution limit. Also, the formation method of the electrode which is connected to the contact hole has come to its limit due to its covering capability and contacting capability.
The conventional emitter formation method is disclosed in the specifications of U.S. Pat. No. 4,814,846 granted to Matsumoto et al under the title of "PHOTOELECTRIC CONVERTING DEVICE" and U.S. Pat. No. 4,816,899 also granted to Matsumoto et al under the title of "PHOTOELECTRIC CONVERTING", for example. There are also emitter formation methods disclosed in Japanese Patent Laid-Open Application Nos, 61-184872 and 62-179760, for example.
Among the emitter formation methods, there is One called "washed emitter process".
FIG. 1 is a schematic view showing a semiconductor device fabricated using the conventional washed emitter process.
Now, for example, the structure of a semiconductor device including an emitter portion is shown in FIG. 1, in which a reference numeral 501 designates a semiconductor substrate; 502, an N-type buried area formed to reduce collector resistance and N-type area formed to lead out a collector electrode; 503, an N.sup.- area; 504, an element separation area formed by oxidation film; 505, a P-type base area; 506, an insulating film; 507, an N-type emitter; 508 and 509, electrodes. With this structure, the emitter size and contact size are of the same value to provide an advantage in the miniaturization of the device.
The fabricating processes therefor will be described briefly. At first, on the semiconductor substrate 501, there are formed the N-type varied area 502, N-type area 503, element separation area 504, base area 505, and insulating film 506. Then, a part of the insulating film 506, on which the emitter must be formed, is removed.
Subsequently, with the insulating film 506 used as a mask, ion is injected to induce impurity and others. Then, a heat treatment is given to form the reverse conductive type emitter area 507 in the base area 505.
After that, the emitter electrode 508 is formed.
Nevertheless, there are still some technical problems to be solved for this method.
One of the problems is that this method requires the introduction of impurity (ion injection) subsequent to the etching of the insulating film 506 and then the impurity is activated by a heat treatment, thus necessitating the high temperature heat treatment which results in the external diffusion of impurity to make the transistor characteristics unstable. Another is that as the circuit integration becomes higher (finer), it becomes more difficult to make the emitter diffusion sufficient, and the resultant lateral diffusion of, the emitter is not good enough and causes the emitter electrode 508 and the base diffusion layer 505 to be short circuited, thus lowering the yield of transistors.